1. Field of the Invention
The present invention relates to digital computation circuits and, more particularly, to a carry select multiplexer for use with a high speed adder.
2. Prior Art
The heart of any computer or microprocessor is the processor itself. One primary function of any processor is its ability to perform arithmetical or logical operations on various inputs to the processor. Various schemes are known in the prior art to provide such arithmetic and logic operations. One necessary arithmetic function inherent in most processors is the ability to add two digital numbers. Throughout the development of processors, the emphasis has constantly been placed on increasing the speed of operation of the processor and components within such processors.
Because many mathematical operations performed by a processor involve iterative computations, the more recent processors implement a number of simultaneous parallel operations in order to decrease the actual iterative cycle. For example, in one prior art scheme, in carrying out an addition operation of two binary numbers, a carryin to a given stage is needed prior to calculating and deriving the sum and carryout from that stage. In a different scheme, the more recent processors utilize the parallel operation technique wherein two adders are provided for each stage. One adder assumes a carryin value of zero while the second adder assumes a carryin value of one. The summation operation is performed and the results from the two adders are determined, wherein the carry input from the previous stage is used to select the proper adder output from that stage. One such selection means is known as a carry select multiplexer, wherein the carryin to a given stage determines which adder output is selected as the output from that stage.
It is to be appreciated that any time savings which can be obtained in any of the operations performed by an adder, will ultimately result in a decrease in the overall computation time for a given processor. Accordingly, any decrease in the time required to select a carry to the next stage will also result in the reduction of time in performing computations within the processor. Consequently, it will be appreciated to those skilled in the art that the reduction of the delay inherent in any stage of the carry select circuitry will improve the speed of operation of a processor. Additionally, improving the speed of an adder is especially important when the adder is on the same integrated circuit chip as other circuits, such as in a microprocessor chip which includes other processing functions, because the time needed to perform the addition provides the dominant delay, rather than the inter-chip communication time. Therefore, any reduction in the computation time or the output selection time will improve the overall speed of the processor.